1. Technical Field of the Invention
The present invention relates generally to very high performance microelectronic chips used in computers, microprocessors, microcontrollers, sensors, communication devices and the like. In particular, the invention relates to the interconnect wiring networks on such chips, with the goal of significantly reducing the signal propagation delay associated with these wires in the networks using copper wiring embedded in a very low k dielectric medium possessing engineered porosity formed after the interconnects are formed.
2. Description of the Background Art
High performance microprocessor, microcontroller and communication chips require very high speed interconnects between the active transistor devices which are used to perform the various functions such as logical operations, storing and retrieving data, providing control signals and the like. With the progress in the transistor device technology leading to the present ultra large scale integration, the overall speed of operation of these advanced chips are beginning to be limited by the signal propagation delay in the interconnection wires between the individual devices on the chips. The signal propagation delay in the interconnects is dependent on the RC product wherein, R denotes the resistance of the interconnect wires and C represents the overall capacitance of the interconnect scheme in which the wires are embedded. Use of copper instead of Al as the interconnect wiring material has allowed the reduction of the resistance contribution to the RC product.
The current focus in the microelectronics industry is to reduce interconnect capacitance by the use of lower dielectric constant (k) insulators in building the multilayered interconnect structures on chips.
One prior art method of creating interconnect wiring network on such small a scale is the dual damascene (DD) process schematically shown in FIG. 1. In the standard DD process, an inter metal dielectric (IMD), shown as two layers 1110, 1120 is coated on substrate 1100 as depicted in FIG. 1a. The via level dielectric 1110 and the line level dielectric 1120 are shown separately for clarity of the process flow description.
In general, these two layers can be made of the same or different insulating films and in the former case applied as a single monolithic layer. A hard mask layer or a layered stack 1130 is optionally employed to facilitate reactive ion etch selectivity and to serve as a polish stop. The wiring interconnect network consists of two types of features: line features that traverse a distance across the chip, and the via features which connect lines in different levels of interconnects in a multilevel stack together. Historically, both layers are made from an inorganic glass like silicon dioxide (SiO2) or a fluorinated silica glass (FSG) film deposited by plasma enhanced chemical vapor deposition (PECVD).
In the dual damascene process, the position of the lines 1150 and the vias 1170 are defined lithographically in photoresist layers 1500 and 1510 respectively, FIGS. 1b and 1c, and transferred into the hard mask and IMD layers using reactive ion-etching processes. The process sequence shown in FIG. 1 is called a “line-first” approach.
After the trench formation, lithography is used to define a via pattern 1170 in the photoresist layer 1510 and the pattern is transferred into the dielectric material to generate a via opening 1180, FIG. 1d. 
The dual damascene trench and via structure 1190 is shown in FIG. 1e after the photoresist has been stripped. This recessed structure 1190 is then coated with a conducting liner material or material stack 1200 that serves to protect the conductor metal lines and vias and serves as an adhesion layer between the conductor and the IMD. This recess is then filled with a conducting fill material 1210 over the surface of the patterned substrate. The fill is most commonly accomplished by electroplating of copper although other methods such as chemical vapor deposition (CVD) and other materials such as Al or Au can also be used. The fill and liner materials are then chemical-mechanical polished (CMP) to be coplanar with the surface of the hard mask and the structure at this stage is shown in FIG. 1f. 
A capping material 1220 is deposited as a blanket film, as is depicted in FIG. 1g to passivate the exposed metal surface and to serve as a diffusion barrier between the metal and any additional IMD layers to be deposited over them. Silicon nitride, silicon carbide, and silicon carbonitride films deposited by PECVD are typically used as the capping material 1220. This process sequence is repeated for each level of the interconnects on the device. Since two interconnect features are simultaneously defined to form a conductor in-laid within an insulator by a single polish step, this process is designated a dual damascene process.
In order to lower the capacitance, it is necessary to use lower k dielectrics such as organic polymers and spin on organo-silicate glasses which have k values in the 2.5 to 3.0 range instead of the PECVD silicon dioxide based dielectrics (k=3.6 to 4.0). The k value can be further reduced to 2.2 (ultra low k) and even below 2.0 (extreme low k) by introduction of porosity in these insulators. The minimum value of the dielectric constant is 1.0. For the purpose of brevity, we shall refer to these ultra low k and extreme low k materials collectively as very low k materials (i.e., in the range of about 2.2 and below) in this document.
Although a tunable range of k values is possible with this set of very low k materials, there are several difficulties in integrating these materials with copper interconnects by the dual damascene process described above.
These low k dielectrics have a much lower elastic modulus, fracture toughness and cohesive strength than the silicon dioxide or FSG films and their adhesion to typical hard mask layers used in current state of the art copper interconnect is also correspondingly inferior. As a result, when the CMP of the copper fill is attempted during the dual damascene interconnect build, delamination occurs either cohesively in the weak low k material or adhesively at the interface between the very low k material and the hard mask. This renders the DD process highly impractical from the point of view of manufacturability and yields.
There are other issues associated with integrating very low k porous dielectrics with interconnected porosity that pertain to the metallization and plating of wiring layers.
In particular, deposition of barrier layers such as tantalum, tantalum nitride, tantalum silicon nitride, titanium silicon nitride, tungsten and tungsten nitride and the like by chemical vapor deposition or atomic layer deposition can lead to the penetration of the gaseous precursors used into the pores resulting in the deposition of the conductive barriers in these pores. This in turn can lead to line to line shorting. Poor coverage of the rough surfaces of the porous dielectric surfaces by these barriers can also lead to infiltration of the plating and cleaning solutions into the dielectric. Poor coverage can also lead to Cu diffusion into the dielectric during subsequent thermal processing cycles which can cause a degradation in the electrical breakdown behavior of the intermetal dielectric (IMD).
One prior art method to overcome some of these difficulties is described in assignee's U.S. Pat. No. 6,451,712 (Dalton et al.), the contents of which are hereby incorporated by reference herein.
In this method, the pore generating component (known as porogen) used in the porous dielectric formulation is retained in the dielectric film during the dual damascene patterning, barrier/liner deposition, plating and CMP so that these steps are performed in a nonporous dielectric. Subsequent to the CMP step, the porogen is removed from the dielectric by a thermal anneal rendering the dielectric porous. This method requires that the hard mask used in the DD fabrication be not only a good CMP stop layer but also be permeable to the porogen species during the thermal anneal step. Further, it is required that the dielectric be able to release the porogen without significant shrinkage so that dimensional changes or thermal stresses in the interconnect is avoided. These requirements are often conflicting in nature and are restrictive of the extent of porosity that can be generated and hence the lowering of the dielectric constant of the IMD. The pores formed are in general randomly oriented and have a range of sizes. Such a porous structure is generally weaker in mechanical strength and sometimes exhibits spatial variability in the dielectric properties as a result of the pore size distribution.
A second prior art method described in a copending patent application Ser. No. 10/280,283 circumvents the issues of porous IMD integration by building the interconnects by a dual damascene process in a support dielectric, etching out the said support dielectric form between the lines only, filling the etched out gaps with a porous low k dielectric and polishing back to planaraize the top of the interconnects.
While this prior art method does avoid all the issues associated the direct DD integration of the porous IMDs, it requires that the porous IMD be able to fill line to line gaps and withstand CMP planarization which can restrict the choices of the porous IMD. Further, additional process steps to etch the support dielectric and fill and polish the gapfill porous dielectric are needed which can add to manufacturing cost and lead to possible reduction in yield.
It is therefore an object of this invention to produce an interconnect structure with very low effective dielectric constant (hereinafter “keff”) by avoiding the above described issues associated with porous dielectrics and the prior art methods of forming integrated structures using them.
It is further an object of this invention to overcome these difficulties, by performing all the steps required for interconnect fabrication using a dielectric without any porosity (robust enough to withstand state-of-the-art semiconductor interconnect fabrication techniques) and introducing nanoscale porosity with controlled size and orientation into it after the dual damascene interconnect structure is formed.